MOESI on an otherwise-similar model.Ĭhoice of MESIF vs. I didn't look for any academic papers that simulated MESI vs. What are the latency and throughput costs of producer-consumer sharing of a memory location between hyper-siblings versus non-hyper siblings?. That's why the inter-core latency for Ryzen has another step from core #3 to core #4.)īTW, notice that the latency between two logical cores on the same physical core is much lower for Intel and AMD. Ryzen has clusters of 4 cores that share an 元. Obviously there are many other differences between Intel and AMD designs that affect inter-core latency, like Intel using a ring bus or mesh, and AMD using a crossbar / all-to-all design with small clusters. many-core Intel (ring bus: Broadwell) vs. For example, see this graph of inter-core latency for Ryzen vs. Wikipedia's MESIF article (linked above) has some comparison between MOESI and MESIF.ĪMD in some cases has lower latency for sharing the same cache line between 2 cores. Which cache mapping technique is used in intel core i7 processor?) Until Skylake-AVX512, the large shared 元 cache was inclusive. Forwarding apply between sockets in a multi-socket system. (Intel since Nehalem already uses a single large shared 元 cache for all cores, so all requests are ultimately backstopped by one 元 cache before checking memory anyway, but that's for all cores on one socket.
MESIF allows caches to Forward a copy of a clean cache line to another cache, instead of other caches having to re-read it from memory to get another Shared copy. The Owned state keeps track of which cache is responsible for writing back dirty the data. The linked wiki article has a bit more detail, but it's basically about sharing dirty data. MOESI allows sending dirty cache lines directly between caches instead of writing back to a shared outer cache and then reading from there. (I don't know about non-x86 cache details.)
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